1. Field of the Invention
The present invention relates generally to methods for the growth of single crystal material layer on complementary metal oxide semiconductor (CMOS) devices.
2. Description of the Related Art
Single crystal materials are used in a number of applications that can be integrated with CMOS circuitry, including photodetectors, LEDs, lasers, resonant tunneling devices, SiGe MODFETs, silicon MOSFETs, ferroelectric sensors, etc. Devices fabricated in these single crystal materials are typically connected to CMOS circuitry either by wire bonding, flip chip bonding, or bump bonding. It is desirable to have the capability to form devices in single crystal material layers directly overtop of CMOS circuitry for a number of reasons. One example is that it is desirable to have photodetector current generating regions located above the CMOS circuitry because of improved photodetector fill factor (there will not be metal interconnects to block the absorption of photons and room needed for readout transistors at the pixel site) and also material layers with optimized optical absorption characteristics (different from the absorption characteristics of silicon needed to fabricated the CMOS circuitry) are desirable. It is desirable to have surface emitter lasers and edge emitter lasers formed directly overtop of CMOS circuitry to implement free space optical interconnects for transmitting digital data off of a CMOS circuit. It is desirable to have waveguide optical modulators and waveguide optical switches integrated directly over CMOS circuitry. In the case that the optical modulators and switches are integrated directly over CMOS circuitry, then there will be only be a small amount of parasitic capacitance that the CMOS circuitry has to drive and secondly, the CMOS circuitry can easily address a two dimensional array of optical switches and optical modulators. In all of the above examples, the ability to integrated photodetectors, lasers, optical modulators, optical switches directly over CMOS circuitry will lead to improved manufacturing process, lower manufacturing cost, and improved reliability compared to flip chip or bump bonding processes.
The typical way of processing a CMOS circuit is to cover the polysilicon gate electrodes and metal interconnects by an amorphous oxide layer or nitride layer. Because of the amorphous nature of the dielectric layer that covers the CMOS material layers, it is typically not possible to grow a single crystal material layer on top of an amorphous material (oxide or silicon nitride) layer over CMOS circuitry.
U.S. Pat. No. 5,374,564 to M. Bruel describes a method of fabricating silicon-on-insulator (SOI) layer that involves combining wafer bonding with a hydrogen implantation and separation technique. The hydrogen implantation and separation technique utilizes a heavy dose of implanted hydrogen together with subsequent annealing to produce H exfoliation that releases the host substrate to generate the SOI structure. The surface following exfoliation has a microroughness of about 8 nm, and must be given a slight chemomechanical polish to produce a prime surface. This step degrades the Si layer thickness uniformity and makes the process unsuitable for producing very thin Si films.
It has been found experimentally that there are a number of techniques to either reduce the required hydrogen ion implantation dose or to reduce the temperature needed to cause hydrogen ion implantation substrate layer splitting process to work. One technique involves the use of a high pressure nitrogen gas stream directed towards the side of a silicon substrate into which a high dose hydrogen ion implantation has been made. It has been experimentally found that the hydrogen ion implantation substrate layer splitting process can occur at room temperature for the case of a silicon substrate into which a high hydrogen ion implantation dose has been made using the high pressure nitrogen gas stream method. It has also been found experimentally that a helium ion implantation made in combination with a hydrogen ion implantation can be used to achieve a lower total implanted dose for the substrate layer splitting process to occur for a given anneal temperature. It has also been found experimentally that a lower substrate layer splitting temperature is achieved for the case that a hydrogen ion implantation is made into a silicon substrate having a high boron concentration. The high boron concentration can be incorporated into a silicon substrate by ion implantation. The lower temperature for hydrogen ion implantation substrate layer splitting to occur is obtained both for the case that the boron implant is annealed and for the case that the boron implant is unannealed.
One way that has been investigated for transferring thin layer of GaAs from one substrate to a second substrate is the epitaxial lift-off technique. In this approach, a GaAs layer is grown on top of a thin AlAs layer that is grown on a GaAs substrate. Thin layers of GaAs have been produced by lateral undercutting an AlAs layer in a dilute hydrofluoric acid etch and then transferring a GaAs epitaxial layer to another substrate using a thick wax to support the thin GaAs layer during the transfer operation. Typically, only small areas (&lt;100 micrometer square) of thin GaAs can be transferred using the epitaxial lift-off techniques and thus is not suitable for full wafer transfer.
A second technique of transfer a single crystal layer to a second substrate is to use an etch stop technique. In the etch stop technique, the wafer is thinned from the backside to within approximately 50 micrometers of the etch stop layer and then the GaAs substrate is etched, stopping at an AlGaAs etch stop. The AlGaAs etch stop is next etched leaving a thin semiconductor layer. The etch stop technique suffers from non-uniform etching of the etch stop layer.
Present methods for growing heterojunction single crystal materials for use have significant shortcomings. The difference in lattice constant between two different single crystal layers can cause significant level of defects in an epitaxial layer grown on a substrate with a different lattice constant in the case that the critical thickness for a given lattice mismatch is exceeded. For instance, the most common method of growing HgCdTe on silicon is to grow CdTe on the &lt;211&gt; surface of silicon, and then to grow HgCdTe on the CdTe layer. However, this process results in a large number of crystal defects in the CdTe layer because of the large lattice mismatch between CdTe and silicon.
One way to reduce the effect of lattice mismatch in the growth of an epitaxial layer on a substrate with a different lattice constant is to use the concept of compliant substrates. Ultra-thin semiconductor layers are required for compliant substrates. In the compliant substrate approach, the ultra-thin semiconductor layer will expand or contract as a heteroepitaxially layer is grown on the surface of the ultra-thin semiconductor layer so that defects, if created, will reside in the ultra-thin semiconductor layer. The principal technique investigated to date for complaint substrate is the twist bonding technique. A second technique involves the use of a low viscosity material between the ultra-thin compliant layer and the handle substrate. Some examples of materials that become viscous at low temperature include boron oxide at approximately 450.degree. C. In addition, metals, eutectics, and solders have a large range of melting temperatures ranging from 156.degree. C. for indium to greater than 1000.degree. C. for other metals. Glasses and oxides also have a wide range of melting temperatures ranging from below room temperature to greater than 1100.degree. C. for fused quartz. The thin compliant layer will expand or contract during epitaxial layer growth and is susceptible to buckling of the thin compliant layer.
In order to direct bond two substrates, it is typically necessary that the surface roughness be less than 10 angstroms rms on each of the surfaces of the substrates. An approach that can be used to obtain less than 10 angstrom rms surface roughness on a CMOS circuit is to use chemical mechanical polishing of the amorphous oxide or nitride layer on the surface of the CMOS circuitry. There are a number of approaches that can be utilized to bond two substrates to reduce the requirement that the two substrate surfaces be polished to an RMS roughness of less than 1 nm. One approach is to deposit a material such as polysilicon, silicon dioxide, silicon nitride, or metal on the substrate surface, and then polish the material to a surface roughness of less than 1 nm RMS. The use of pressure, temperature, or vacuum separately or in combination also reduces the requirement to have a surface polishing of 1 nm or less. If one of the substrates is thin, then the thin substrate will more easily conform to the other substrate during bonding and thus reduce the requirement for surface roughness less than 1 nm RMS. Metals can be deposited on the substrate surface and the metals will bond to the second substrate surface with the help of pressure, temperature, and vacuum possibly by forming a eutectic with the second substrate material. Metals can be deposited on both substrate surfaces and bonded. Brazing or soft solder materials can be deposited on one or both surfaces and the substrates bonded. Preceramic polymers can be used to bond two substrates. Ceramic materials can be deposited on one or both substrate surfaces, the substrates heated to the melting point of the ceramic material sometime under pressure, and the two substrates bonded. Materials such as silicon and germanium that melt during bonding and react with the substrate material can be used to bond two SiC substrates together. Electrostatic or anodic bonding can be used to bond a substrate to an alkali containing glass material. In some cases, alkali containing glass can be deposited on one surface by sputter or evaporation and anodic bonding. A rough surface can be coated with a spin-on-glass to achieve a surface smooth enough for bonding. A low melting point frit or solder glass can be deposited on a surface and bonded to a second surface using pressure and temperature. A sodium silicate material deposited on a substrate surface will aid bonding. Bonding approaches that are appropriate for lower temperatures include polymer adhesive, organic adhesive, and epoxy bonding. The ambient is sometimes important during the bonding operation. For bonding of GaAs substrates, it is generally preferred to have a hydrogen ambient during bonding.
Because of reaction of metal interconnects with the silicon layer in the source and drain regions, the typically maximum temperature that a CMOS circuit can be exposed to is approximately 500.degree. C. to 550.degree. C. Some CMOS processes use barrier metals such as titanium tungsten between the metal interconnect and the silicon source and drain regions which will help prevent the interaction of the metal interconnects with the silicon source and drain regions. If metal interconnects are not present on the CMOS circuit, then the maximum temperature that a CMOS circuit can be exposed to is limited by the diffusion of the source and drain dopants and is approximately 900.degree. C. to 1000.degree. C. for a short time period. There are a number of epitaxial materials that can be grown at less than 500.degree. C. to 550.degree. C. temperature range including GaAs, GaSb, InGaAs, SiGe, CdTe, and HgCdTe.
Prior to epitaxial growth on a single crystal layer, there is typically a processing step to desorb native oxide from the single crystal layer. For a single crystal silicon layer, a anneal in an vacuum at approximately 500-550.degree. C. for 15 seconds is needed to desorb the native oxide layer. For GaAs, an anneal of 500-550.degree. C. for 15 seconds is also needed to desorb the native oxide layer.
Waveguide optical modulators and waveguide optical switches can be made using epitaxial growth of multiquantum well material layers on GaAs and InP single crystal substrates. These modulators typically operate as an electroabsorption waveguide modulator or utilize the Wannier-Stark effect to modulate the optical waveguide. A common multiquantum well material layer for modulators on InP substrate is InGaAsP/InP material system. The metal electrodes for modulating the electric field in the heterojunction material are typically arranged on the surface of the grown material. Ridge waveguides are typically formed by having higher index of refraction materials on the top and bottom surface of the waveguide and appropriately etching the semiconductor material.
Surface and edge emitter lasers are typically made in III-V material systems by appropriately confining the current flow and designing the index of refraction of the material layers to guide the reflections the generated laser light. The surface emitting laser typically requires a backside mirror layer.
Present methods for growing single crystal materials for use in these applications have significant shortcomings. For instance, the most common method of growing HgCdTe on silicon is to grow CdTe on the &lt;211&gt; surface of silicon, and then to grow HgCdTe on the CdTe layer. However, this process results in a large number of crystal defects in the CdTe layer, because of the large lattice mismatch between CdTe and silicon.
The most common way of making infrared focal plane arrays is to form HgCdTe detector material on one substrate, the CMOS readout circuitry on a second substrate, and to connect the CMOS readout circuitry to the infrared detector by bump bonding. Unfortunately, bump bonding has reliability problems, especially for large area detector arrays.
Infrared focal plane arrays can also be made by forming interconnects on the front side of the detector to CMOS readout circuitry, but the area taken up by the interconnects detracts from the packing density of detectors in these focal plane arrays.
Three-dimensional CMOS integrated circuits are desired for increased processing functionality. Processes that have been presented for fabrication of three-dimensional CMOS circuits (M. B. Kleiner, et. al., Thermal Analysis of Vertical Integrated Circuits" 1995 International Electron Device Meeting, pp. 487-490) have included the fabrication of CMOS circuits on separate wafers, the thinning of a CMOS wafer from the backside to approximately 10 micrometer thickness, the stacking of the thinned CMOS wafer on top of a second wafer using a glue as the bonding mechanism, and the formation of vias and metal interconnects from one wafer to the next wafer.